There are two interrelated device parameters to be concerned during SRAM cell design: read stability (hereinafter “stability” or “cell stability”) and static noise margin (hereinafter “SNM”). Stability indicates how likely it is to invert the stored value of a SRAM cell when accessing it. SNM refers to the minimum DC noise voltage necessary to flip the state of the cell. Between these two parameters, stability is even more important.
As cell technology is scaled, cell power supply voltage (Vdd) is reduced for the purpose of ensuring proper operation of the complementary metal-oxide-semiconductor (CMOS) device and to minimize stand-by and active power consumptions. In order to maintain good SRAM cell performance with the reduced power supply voltage, it is also desirable to scale the threshold voltages (Vt) of the metal-oxide-semiconductor field effect transistors (MOSFETs) contained by the SRAM cell.
However, Vt variations, especially random Vt variations, do not readily scale with Vt. In general, variations in device characteristics include both systematic variations and random variations. Systematic variations (or process variations) are variations in a manufacturing process that equally affect some or all elements of a local circuit, depending on, for example, the orientation, geometry, and/or location of an element. Systematic variations typically have significant spatial correlations, and elements that are near each other can be expected to have the same or similar amount of systematic variations. Therefore, body-biasing methods can be readily used to compensate for the system variations. In contrast, random variations in device characteristics are uncorrelated. Such random variations can adversely affect circuit behavior even more drastically than systematic variations in circuits such as SRAM cells, and more importantly, they are very difficult to control.
Vt variations between neighboring MOSFETs have major impacts on the stability and SNM of SRAM cells. More specifically, Vt variations between the pass-gate transistors and the pull-down transistors of a SRAM cell can significantly degrade the cell stability, especially when the input and output transition of the pass-gate transistors are rising from a low state (the ground voltage) to a high state (the word line voltage). When the word line is at a high state characterized by the word line voltage, the gate electrodes of the pass-gate transistors are at the same high state with the same word line voltage, and output of the pass-gate transistor is limited by the threshold voltage, i.e., the output is substantially equal to the difference between the word line voltage and the threshold voltage. Therefore, any small variations in the threshold voltage will result in a large variation in the currents that flow through the pass-gate transistors and the pull-down transistors, which in turn leads to reduction in the cell stability.
There is therefore a need for methods and apparatuses that improve cell stability of the SRAM cells. There is also a need for methods and apparatuses that improve SNM of the SRAM cells.